IBIS Macromodel Task Group Meeting date: 22 October 2013 Members (asterisk for those attending): Agilent: * Fangyi Rao * Radek Biernacki Altera: * David Banas Julia Liu Hazlina Ramly Andrew Joy Consulting: Andy Joy ANSYS: Samuel Mertens * Dan Dvorscak Curtis Clark Steve Pytel Luis Armenta Arrow Electronics: Ian Dodd Cadence Design Systems: Terry Jernberg * Ambrish Varma Feras Al-Hawari * Brad Brim Kumar Keshavan Ken Willis Cavium Networks: Johann Nittmann Celsionix: Kellee Crisafulli Cisco Systems: Ashwin Vasudevan Syed Huq Ericsson: Anders Ekholm IBM: Greg Edlund Intel: Michael Mirmak Maxim Integrated Products: Mahbubul Bari Hassan Rafat Ron Olisar Mentor Graphics: * John Angulo Zhen Mu * Arpad Muranyi Vladimir Dmitriev-Zdorov Micron Technology: * Randy Wolff Justin Butterfield NetLogic Microsystems: Ryan Couts Nokia-Siemens Networks: Eckhard Lenski QLogic Corp. James Zhou SiSoft: * Walter Katz * Todd Westerhoff Doug Burns * Mike LaBonte Snowbush IP: Marcus Van Ierssel ST Micro: Syed Sadeghi Teraspeed Consulting Group: Scott McMorrow * Bob Ross TI: Casey Morrison Alfred Chong Vitesse Semiconductor: Eric Sweetman Xilinx: Mustansir Fanaswalla Ray Anderson The meeting was led by Arpad Muranyi ------------------------------------------------------------------------ Opens: - Walter: We should discuss the enhancements needed to handle die pad to pin hookups and NEXT/FEXT. - This should be about requirements, not proposed protocols. -------------------------- Call for patent disclosure: - None ------------- Review of ARs: - Arpad request people to create ideas for new interconnect examples - Done ------------- New Discussion: Interconnect examples: - Walter: No new examples have come in from the email list. - Randy has an on-die RDL example we could look at. - Arpad showed his request email to the list, which requests an example. - Walter: I can create syntax for that request. - We must agree that the IBIS [Component] section must change to support this. - Would prefer to defer this until after the RDL discussion. - Brad: Cadence Japan is a member of JEITA - They may be able to share something about LPB, will check. AR: Brad check on JEITA LPB information from Cadence Japan - Brad: Is stacked die a subset on 1-to-N and N-to-1 connections? - Arpad: Yes, it can be a different challenge where it is known that there are different die. - Walter: The difference is in the interface. - With stacked memory all pins are stacked except chip select. - Also there can be M-to-N for power and ground. - We must decide what we want to support - John: Many tools support EBD assuming more than one buffer behind each pin. - Walter: EBD and EMD can address this. - We must decide what we want [Component] to support. - Arpad: If EMD brings in multiple die and package elements it confuses the idea of what a package is. - Walter: Do we want [Component] to always represent one pin and one buffer? - Arpad: How will we model pins that have two buffers behind them? - Walter: That will require EMD or EBD. - It is rare to have one buffer connected to two pins. - John: We probably can have that with [Circuit Call]. - Mike: Components have to be easily assigned, EBD is for multi-board systems. - Multi-board systems require more setup. - The most useful model is a component that needs only to be assigned. - Walter: A multi-chip modules can look like a component but represented by an EMD file. - Arpad: Are we ready for a vote? - Walter: We could have separate votes on the following capabilities: 1) Shall an IBIS Component be enhanced to support stacked (N) memory chips? 2) Shall an IBIS Component be enhanced to support a different number of supply pins and die pads? 3) Shall an IBIS Component be enhanced to support single pins connected to N instances of the same buffer? 4) Shall an IBIS Component be enhanced to support single pins connected to N instances of different buffers? 5) Shall an IBIS Component be enhanced to support N pins connected to a single buffer? 6) Shall IBIS package and on-die interconnect models be associated with IBIS Models? 7) Shall IBIS package and on-die interconnect models be associated with IBIS Model Types Input (FEXT) and Output (NEXT)? - Arpad: We could vote here or by email. - Bob: We should discuss having a "super component" with access within. - John: This is more about changing .ibs than about a successor to EBD. - Modifications to [Pin] would be a bad idea. - Bob: EMD should be a separate issue, it will have its own problems. - If we vote by email should it be secret ballot? - Arpad: We should take one vote per company. - Walter motioned to vote on the 7 questions by email - There were no objections. AR: Arpad call for email vote on 7 questions Description of RDL: - Randy: RDL stands for Re-Distribution Layer. - It is used for example to connect center-die signals to the edge. - It is added on after the wafer is made. - Signals want to go across the top, power and ground can be done with vias. - Bond pad to buffer routing is not RDL. - Brad: Agree with this description. - Walter: Xilinx referred to RDL, but it was part of the die. - Brad: Die features are about 1 micron, but RDL is much larger. - Some people associate it with the chip, others the package. - Randy: Die edge pads might be called die pads even if formed with RDL. ------------- IBIS Interconnect SPICE Wish List: 1) Simulator directives